Features: VDD = VDDQ = 1.5V ±0.075V1.5V center-terminated push/pull I/ODifferential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#)8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Programmable CAS READ latency (CL)Posted CAS additive latency (AL)Programmable CAS WRITE latency (CWL) based on tCKFixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])Programmable CAS latency.